The invention relates to a multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device and to a memory system including a multi-level memory device and such a multi-stage codeword detector. Further, the invention relates to a method for operating a multi-stage codeword detector and to a computer program for executing such a method. Particularly, the multi-level memory device includes multi-level cells (MLC) having a plurality of programmable levels.
A prominent example for MLC memory cells having a plurality of programmable levels is Resistive Random Access Memory (RRAM; see reference [3]), particular Phase Change Memory (PCM; see reference [2]), or Flash (see reference [1]). PCM is a non-volatile solid-state memory technology that exploits a reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM may be considered a prime candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology may be multi-level cell functionality, in particular for low cost per bit, and high-speed read/write operations, in particular for high bandwidth. Multilevel functionality, i.e., multiple bits per PCM cell, may be a way to increase storage capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e., memory programming, may be enabled by Joule heating. In this regard, Joule heating may be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task.
In MLC PCM, the physical quantity measured during cell readout, i.e., the electrical resistance drifts upwards with time following a deterministic empirical power-law with stochastic fluctuations. In MLC Flash, the physical quantity measured is the transistor's threshold voltage, which in turn increases with the number of program/erase cycles. Moreover, in solid-state memory technologies, the read signal is hampered by noise having RTN signature and 1/f characteristics (see reference [4]). In order to increase the reliability of such devices, it may be necessary to use advanced signal processing and/or coding techniques that allow the estimation and detection of the stored information levels (see references [5]-[7]). These types of signal processing functions use as input the soft-information from the readout signal and typically operate on a data-block basis, i.e., on a group of read-out values. The requirement for using advanced signal processing in the read process introduces latency and most probably data overhead which have to be kept at minimum level for solid-state memory applications. In this context, careful design of the memory system architecture may be a key factor to achieve maximum performance with minimum circuit complexity.
On readout of multi-level cells, the read signal level is compared with a set of reference signal levels indicative of the q cell-levels in order to determine which level each cell is set to and thus detect the stored symbol value. However, a problem in multi-level memory devices is that the physical quantity measured during cell readout, such as electrical resistance in PCM devices, may have been changed from its nominal value, i.e., due to noise and/or other physical effects. In particular, the electrical resistance of PCM cells drifts upwards with time in a stochastic manner. This drift can be data-dependent, i.e., may vary for different cell levels. As another example, in flash memory cells the physical quantity measured is the transistor's threshold voltage and this increases with the number of write/erase cycles the cell is subjected to. For any given stored symbol value and hence cell level, therefore, the actual read signal level obtained on cell-readout is variable.
Drift in PCM is a serious problem for multi-level storage in that it severely compromises reliability. The readback values of neighboring levels may interfere over time, due to upward drift of the lower level towards the upper level, causing detection errors. Hence packing higher numbers of levels per memory cell becomes more difficult due to the increased likelihood of error during detection. On the other hand, packing more bits per cell is a crucial requirement for all memory technologies, being the best known way of reducing manufacturing cost per bit. Hence, in situations like this where the read signal level distributions for cell-levels are varying, the reference signal levels used for level detection need to be varied as well, e.g., with time, or with the number of write cycles, etc. Reliable estimation of the reference signal levels is crucial to reliable readback performance.
One approach to the above problem uses training data derived from a pool of reference memory cells for drift estimation. Known information is written to some of these reference cells each time a block of user data is written to memory. These reference cells are then read whenever the user file is read, and the reference cell readings are used to derive estimates for the changing reference signal levels used for detection of the user data. Use of a large amount of this training data significantly reduces storage capacity, while reducing the amount of training data reduces accuracy of level estimation. There is also a penalty in terms of controller complexity and latency due to readout of the extra cells, as well as issues, e.g., wear-leveling issues, related to management of the pool of reference cells. Further, since drift is a statistical phenomenon and there is significant variability between cells in a memory array, reference cells may not be representative and the effectiveness of this approach may vary substantially with time and over different portions of the memory array.
Model-based drift cancellation techniques provide another approach. These seek to model drift based on key parameters such as temperature, time and wear, and compensate accordingly. It is, however, difficult to obtain an accurate cell history for the key parameters. There are also fluctuations from cell to cell and there is no well-established analytical model available for short-term drift.
WO 2013/046066 A1 discloses a drift-resistant technique for read-detection of permutation-based codes in multi-level solid state storage devices SSSDs. The codes in question are length-K, qary-symbol codes, whereby each codeword has K symbols and each symbol can take one of q symbol values. Each symbol is recorded in a respective q-level cell by setting the cell to a level dependent on the qary symbol value. The detection system exploits the property of permutation-based codes that all codewords are permutations of a known set of K-symbol vectors, e.g., the so-called “initial vectors” for a union of permutation codes. Memory cells are read in batches to obtain read signals corresponding to a group of codewords. Each read signal has K signal components corresponding to respective symbols of a codeword, and these components are ordered according to signal level to obtain an ordered read signal for each codeword. Components of these ordered read signals are related to symbols of the known set of initial vectors via a process which involves averaging ordered read signals and relating the averaged signal components to symbol values using predefined probabilities of occurrence of different symbol values at different symbol positions as derived from the initial vectors. This reduces the problem of finding the q drifted reference signal levels to the problem of solving an over-determined system of K linear equations for the q unknown reference levels.
In this way, estimates are obtained for the reference signal levels for the q-level cells in the current batch, and these reference levels are then used in codeword detection for the batch. Unlike the training-data approach, this is a self-adaptive technique which uses the actual cells storing encoded user data to estimate the reference levels for those cells on readback, thereby accounting for drift effects on a dynamic basis. The technique is also robust and lends itself to simple, fast decoder implementation. However, level-estimation performance can be variable with certain conditions, e.g., depending on the particular code employed, and small batch sizes in particular can adversely affect reliability, especially for “inner” levels of the series of q memory cell levels.
The detection system of WO 2013/046066 A1 comprises two signal processing stages for detecting a respective codeword from a respective received read signal.
Further conventional methods and techniques are described in U.S. Pat. No. 8,289,781 B2, U.S. Pat. No. 7,814,401 B2, U.S. Pat. No. 7,907,444 B2, U.S. Pat. No. 8,156,403 B2, U.S. Pat. No. 8,145,984 B2, U.S. Pat. No. 8,369,141 B2, and U.S. 2013/0086457 A1.